Digital Clock Management Module In The Fpga Design

With the rapid development of PLD (programmable logic device), system design enters the times of SOPC (system on programmable chip). The design of chip trends high density, low voltage, low power. At the same time, we meet with many problems that we have to solve, such as clock; we should design high speed, low skew clock to satisfy these conditions, that's why we write this article.This article emphasises on CSMT's HWD2V1K chip's DCM (digital clock manager). DCM has three important functions: de-skew, frequency synthesis, phase shift. These functions are carried out by DLL (delay locked loop), DFS (digital frequency synthesis), and DPS (digital phase shift), respectively. We will discuss the three modules in detail in this article.First, we should know why we should de-skew, and how to de-skew. We know FPGA has lots of clock buffers and clock routing. When clock passes these buffers, it will produce delay. Sometimes the delay is so big that we can't ignore, because it may produce fatal error. DCM by inserting delay in delay line can solve this problem.We know FPGA can be used in many filed, user can use different clocks. So we need provide a module that can produce kinds of different clock to satisfy user. We know DLL can provide divide clock very well, but DLL can't multiple clock well, such as 4,8,16. DCM by adjusting DFS's M and D parameter can provide different kinds of clock (M and D, 1~32).With the development of FPGA, the clock has very high frequency, so it is difficult to produce phase that user want to get. DCM by adjusting the delay line of DPS provide different clock, which may be divided from CLKIN or multiple from the CLKIN. DPS can provide any phase that user wants.DCM can work between 24MHZ and 230MHZ in low frequency mode, between 48MHZ and 450MHZ in the high frequency mode. DCM takes up area 615μm*530μm. It can works under -40℃~125℃. Its largest jitter input can be 300ps; its largest jitter output can be 300ps.