Skew compensation techniques for multi-gigabit wire-line data communications

In current multi-gigabit wire-line data communication applications, within-pair skew (WPS), also-called intra-pair skew, is defined as a time difference in propagation between two complementary signals transmitted through a differential channel. WPS causes rise time degradation and attenuates high-frequency components of a differential signal. These effects are more severe for higher data rate and longer channels. To remedy WPS, system engineers generally have to choose customized cables and connectors with the same length to keep equal propagation delay between the differential paths. However, this increases physical dimensions of cables as well as system costs. This dissertation presents an automatic WPS compensation technique for high-speed differential links. An adjustable wide-bandwidth data delay element design is proposed to introduce additional amount of delay to the path with leading phase. An on-chip WPS detection circuitry is also presented for automatic close-loop skew compensation. A WPS compensator prototype has been fabricated in 0.13microm standard complementary metal-oxide-semiconductor (CMOS) technology. Measurement results show that the WPS compensator can automatically compensate for +/-UI input skew at 5Gb/s. It consumes 20.4mW from a 1.2V power supply and occupies 0.015mm 2 active die area.;Parallel links are widely used in high-performance computing systems to enable high-throughput data communications. However, mismatches between channels can cause data transmitted in one channel to arrive at a different time with that in another channel. This is referred as between-pair skew (BPS) or inter-pair skew. BPS can significantly reduce the receiver timing margin and limit the data transmission rate. To achieve a higher per pin data transmission rate, either restrictions on channel matching which limits transmission distance, or high-cost high-quality transmission media are enforced to reduce BPS; or per channel clock and data recovery which consumes large power and area is required. To avoid these issues, previous designs have used one local core clock to generate multiple phases. For each channel, the individual clock phase is determined during a calibration period when clock signals are sent along all data lines as training signals. Additional circuits, i.e. additional power, are then needed to align recovered data from all channels. This dissertation describes an automatic BPS compensation technique to thoroughly eliminate sub-bit BPS by aligning each data channel with an exclusive reference channel, no matter clock or data is transmitted. The design has been fabricated in 0.13microm standard CMOS technology, occupies 0.038mm2 active die area, consumes 22.5mW and achieves +/-100ps skew correction at 5Gb/s, which covers an entire bit.