Mobile Multimedia Broadcasting System Channel Estimates And Equalizer Algorithms And Vlsi Implementation

Mobile Multimedia broadcasting is a hotspot recently, which is widely used in the Europe and the US. China released its own mobile multimedia broadcasting standard which is called CMMB (China Mobile Multimedia Broadcasting) in October,2006. From then on, especially after the 29th Olympiad was held in Beijing in 2008, mobile multimedia broadcasting develops fast, with new handheld equipments which support CMMB released frequently. The network of CMMB has covered more than 30 cities and areas.Channel estimation and equalization are key technologies in demodulation of mobile multimedia broadcasting. Its performance directly affects the demodulation of the signals, as well as the receiver performance.This thesis choose two of the main standards——the Chinese CMMB and the European DVB-H——to start the research with. The research mainly includes channel estimation and equalization in the demodulation of the mobile multimedia broadcasting. Firstly, the algorithms and architectures of the two standards are researched separately, as well as their VLSI implementations. Then a common hardware architecture which is compatible for both CMMB and DVB-H is researched.The major work of this thesis includes:(1).Gives a design of channel estimator and equalizer for CMMB. The channel estimator for CMMB in this thesis employs a novel interpolator in time direction which includes two interpolation algorithms to choose according to the actual wireless environment and the mobile speed. The mobile performance of the estimator and equalizer is good. Its typical values of BER are 4×10-3 and 1×10-2 under 15dB SNR using TU-6 channel with 200Hz of Doppler frequency shift in BPSK and QPSK modulation, respectively. Synthesis results by DC (using SMIC 0.13μm process, VeriSilicon components,50MHz clock frequency) shows that its total hardware implementation includes 645 thousand gates. Of the memory it uses,98304 bits are reused in the system——about 125 thousand gates.(2).Gives a design of channel estimator and equalizer for DVB-H. The channel estimator for DVB-H employs widely used two-dimensional linear interpolator, which includes two linear one-dimensional interpolators——the time direction linear interpolator and the frequency direction linear interpolator. Its performance satisfies the requirement of DVB-H. Its typical values of BER are 0.1 and 0.27 under 15dB SNR and 64QAM modulation using TU-6 channel with 20Hz and 200Hz of Doppler frequency shift, respectively. Synthesis results by DC (using SMIC 0.13μm process, VeriSilicon components,50MHz clock frequency) shows that its total hardware implementation includes 780 thousand gates. Of the memory it uses,98304 bits are reused in the system——about 125 thousand gates.(3).Design a power and area efficient architecture of convolver based on ram. It has been taped out and fabricated successfully. Also design a CCI detection and cancellation algorithm which can detect and cancel more than 95% of the errors due to CCI.(4).Design a common architecture for both CMMB and DVB-H standards. The key idea of the common hardware architecture of these two standards is the reuse of their memory. The hardware of the final-architecture which supports both the two standards includes 830 thousand gates. There are total 646592 bits of memory in the architecture. Of these,380096 bits (58%) are reused.