Fpga-based Digital Image Preprocessing Algorithm Research

The high speed of image processing is required in the real-time image processing system. Image processing with software can't meet the demand, so it is mainly implemented by hardware. FPGA is an ideal device for this purpose. At present, the research of image processing based on the FPGA has become a hot topic.This thesis constructs a system based on FPGA hardware to validate the algorithm of image preprocessing. The system is mainly composed of PC, communication module, memory module, image preprocessing algorithm module, FIFO module and control module. Several typical image preprocessing algorithms, such as statistic order filter, median filter, Morphological filter, Gaussian filter, Laplacian and Sobel operator etc, are implemented on the system. In the process of the system design, the characteristics and requirements of the image-processing implemented by hardware are fully considered. The parallel attribute insiding the image algorithm is effectively dug and pipelining structure is adpot. All mentioned above are useful to optimize and improve the algorithms, reduce the hardware consumption and raise speed of image processing.The design, simulation and validation of the whole system are implemented in Verilog HDL on the tool of Quartus II and validated by the hardware platform which is designed based on the chip of EP2C8Q208C8 manufactured in Altera. By analysing the processing result and performance of the image preprocessing algorithm, the image processing implemented by FPGA fully satisfies the requirement of real time.This thesis is a useful attempt for the application of the FPGA in the real-time image processing system. It also has positive meaning in implementing the real-time image processing based on FPGA.