Debugging And Optimization Of Silicon-germanium Epitaxial Process

Epitaxial(Epi) is a process of depositing a thin layer of single crystal material upon a single crystal substrate of similar lattices.Deposited epi layer could be homoepitaxy(Si/Si) or heteroepitaxy(SiGe/Si,SiC/Si,etc.).There are many techniques available to achieve Epi deposition,molecular beam epitaxy(MBE), chemical vapor deposition(CVD),which includes ultra-high-vacuum chemical vapor deposition(UHV/CVD),atmospheric and reduced pressure Epi(ATM & RP Epi),etc.Because of its excellent performance in noise,current gain and linearity, Si_1-xGe_x/Si-based heterojunction-bipolar-transistor(HBT) became the most important achievement in application of strained Si_1-xGe_x/Si material..In addition to those currently existing in many products,SiGe HBT finds more and more applications in many new products.Many communication-product oriented semiconductor companies have incorporated SiGe HBT-in their technology roadmap.But to satisfy device requirement,the Epi growth of SiGe as a base material,must be processed at low temperature,which makes it difficult to be controlled compared with normal high-temperature Epi process.Therefore,in-depth study and optimization of HBT SiGe Epi becomes extremely important.In this thesis,tools and related key parts used in the experiment are introduced, and results of equipment acceptance test are also described.Based on a theory and experience,a screen DOE was designed to study the influence of several process parameters that include temperature,H₂ flow,SiH₄/GeH₄ flow and chamber pressure.Characterization was conducted for SiGe film(thickness, composition).The results can be concluded as follows:(1) Depositing rate of Si cap layer is sensitive to temperature.The depositing rate of Si cap layer increases linearly as temperature increases.Flow rates of SiH₄ and H₂ also have impact on deposition rate of cap layer.Cap layer thickness increases with the increase of SiH₄ flow;while when H₂ flow rate incrases,the cap layer becomes thinner due to the descrease of SiH₄ pressure.Chamber pressure has almost no effects on cap layer deposition rate.(2) Depositing rate of SiGe block layer has no correlation with chamber pressure.But it is influenced by other factors.SiGe block layer thickness increases with the increase of process temperature,GeH₄ or SiH₄ flow rate.Similar as cap layer,thickness of block layer decreases significantly as H₂ flow rate increases.(3) Ge composition(Ge%) of SiGe layer is strongly dependent on the GeH₄ flow. The higher the GeH₄ flow rate,the more the Ge concentration.Ge%decreases with the increase of temperature or SiH₄ flow.Deposition rate increases with the increase of process temperature or SiH₄ flow,which resulting thicker block layer within a specific duration.Because GeH₄ is completely consumed in the deposition reaction, the total amount of reacting GeH₄ does not change if GeH₄ flow keeps unchanged.So that Ge%will be reduced accordingly.Based on the results of the experiments,a recipe of optimized parameters(gas flows,chamber pressure,temperature,etc) was setup for mass production.To meet device specification,target SiGe process should provide gradient Ge%profile and adjustable B₂H₆ concentration.At the beginning,a thin transition layer of pure Si-epi (～230(?)) is deposited.Neither Ge nor B₂H₆ is doped in this layer.Next,a SiGe film with linear Ge%changing,which exhibit asymmetric ladderlike profile,is deposited. In this SiGe layer:the first transitional 120(?),Ge%rapidly increases from 0%to 12%;Ge%keeps at 12%level in the next 230(?);Ge%slowly drops from 12%to 0%in end of this layer.At last,a cap Si layer is deposited to cover the underneath layers.B₂H₆ doping flow varies during the whole deposition process,so does B%. The peak of B%is about 2.5×10¹⁹ atom/cm³.The distance of the B%peak to EB junction(interface) is about 220(?).B%at EB junction is about 4×10¹⁸ atom/cm³. The B and Ge profiles demonstrate continuous change,and no abrupt change is observed.SiGe was used as the base material to form heterojunction in a BiCMOS products of 0.35μm.Experiments of process window were conducted regarding factors of Si cap layer thickness,B%,Ge%and chamber temperature.Process window was further verified through analysis of current amplying numberβ,V_BE, BV_EBO and BV_CEO.At the end of the thesis,issues and solutions in SiGe process development are briefly summarized.The summary covers special patterns in Rs mappping;and general judgement and solution for SiGe process abnormal and defect issues.