Based On Ldpc Codes, Dmb-th Codec Research And Design

Ever since 1948 the foundation of "Information and coding theory" by Shannon, the channel coding technology has become an important part of communications. As Shannon's theory only points out the theoretical limit of reliable communications, for several decades the researchers have been mainly focusing on finding capacity-approaching codes and decoders which are fit for hardware implementation. Nowadays, Low-Density Parity-Check Codes is becoming an important topic in error-correcting codes, because of its outstanding performance and great application potential. LDPC code is used as error-correcting codes in China's terrestrial digital multimedia TV/handle broadcasting (DMB-TH) and China mobile multimedia broadcasting (CMMB), as well as the next generation of digital satellite broadcasting standard (DVB-S2). The DMB-TH standard uses LDPC-BCH concatenated codes as its forward error correction codes.In this paper, after researching the error correction codes, we present the encoding and decoding algorithms and the hardware implement for LDPC based on DMB-TH. First of all, a simple introduction to error correction technology, digital TV, the basic principles of LDPC code and decoding algorithm is proposed. Then a multi-rate memory-efficient encoder for LDPC codes is proposed in this paper based on shift-register-adder-accumulator (SRAA). The SRAA algorithm simplifies the encoder computation module and reduces the complexity of the operation. The multi-rate encoder reuses the SRAA circuits to cut down the number of resource consumption. Simulations demonstrate that the proposed multi-rate encoder can satisfy the DMB-TH with lower complexity.Then we do some simulations on decoding performance of LDPC codes using a variety of decoding algorithms, and simulations show that the performance of the min-sum algorithm is worse 0.7-1.1dB than BP algorithm. As a result, we use the modified min-sum algorithm that is called the normalized min-sum algorithm as the decoding algorithm. With normalized coefficient 0.625, 20 iterations, the performance is only worse about 0.05dB ~ 0.1dB than BP algorithm. Because the check matrix is quasi-cyclical, the partial parallel decoder structure is proposed that makes a better compromise in resources and speed. After the design of the overall structure of the decoder, we focus on the design and implement of the key modules of the decoder, including the variable node processing unit, check node processing unit and memory design. The improved check node processing unit in this paper only consumes about half of the resources of the normal one.