Design And Implementation Of Wimax Baseband Processor Board Dsp Subsystem

World Interoperability for Microwave Access (WiMAX) is a kind of wireless metropolitan area network access technology based on the IEEE802.16 standard, its practical applications to the suburbs has basically been able to cover. WiMAX as a wired network can not only expand wireless access to achieve network connectivity in remote areas, but also access the wireless metropolitan area network. WiMAX Acer station is one of the wireless metropolitan area network applications.A research paper is from ZTE WiMAX Acer Limited Station project, which developed under the 802.16e standard Acer stations, to provide users with stable high-speed communications services. Thesis is about the baseband processor board in the base transceiver stations. Baseband processor board as a baseband processor module of the base station transceiver, its main function is to complete the 802.16e physical layer processing algorithms.Current 802.16e physical layer protocol needs to code and decode, modulateand demodulate the transceiver information, which includes a lot of compute-intensive digital signal processing technology. Because the agreement is growing perfection when the market there is no specialized chip set solution, or a dedicated ASIC chip. Taking into account the above logic is deal with some of the hardware for the realization, some are suitable for the realization of digital signal processors, the single physical layer processing module FPGAs + DSPs is needed for the realization of the program. 4 DSPs and 2 FPGAs are used in this program, a DSP as a master of them, three other DSP and FPGA for algorithm processing. The important works of this paper are as follows:(1) Hardware design and implementation of the DSP subsystem of baseband processor board: the latest technology - Rapid IO is used, 3.125Gbps rate of high-speed of the entire DSP subsystem is realized, and the Gigabit network is designed.(2) Software design, the master DSP supports the upgrading and back of secondary Bootloader; supports the loading algorithm of the DSP and the FPGA version, supports surveillance operation for other DSP and FPGA algorithm, saving the production cost and improve the system stability.(3) For the SRIO and network interface hardware design requirements, the network interface port and SRIO are namely designed and realizated in detail.(4) To algorithm DSP, not only the algorithms are realized, but also a few of the erro control modules which are message reported in support of self-repair mechanisms error are considered. Interleaver algorithm CTC is discussed.Finally, DSP sub-system unit and system are tested; results showed that the sub-subsystem module and the entire sub-system tasks have reached the required functionality.