On-chip Network Topology And Simulation Platform Design

With rapid development of technology, it is possible to integrate multiple cores on one single chip. As the number of cores of system chip increased, traditional SoC design methodology will not fit on-chip multicore communication enviroment. At this time NOC becomes the key solution to on-chip multicore communication, and researches related to NOC soon becomes the frontier and hotspot of the corresponding fields.On this research background, this paper choose NOC topology and its corresponding routing algorithm, and NOC simulation and verification platform as our field of research. In this paper, we mainly discuss the NOC topology, and the design of NOC simulation platform. The main results are as follow:1. Summarized three classical NOC topology in detail, included Mesh, Torus and Hypercube NOC. And evaluated their performance through completely simulation under different traffic pattern.2. Proposed two novel NOC topology: the Multi-Dimension Plane NOC (MDP NOC) and Color-Dormain Hop NOC (CDH NOC). MDP NOC introduces the node indexing of high-dimension topology to 2D plane NOC, brings higher network performance; and CDH NOC refers to the coloring algorithm of graph theory, enhance the scalability of NOC and reduce the resources consumed. Then Evaluated their performance and resources consuming by comparing to some classical NOC.3. Researched the design of NOC simulation and verification platform, include modulazied NOC node structure design, generation of network topology and network traffic. Developed a SystemC-based NOC simulation and verification platform—NSVP. By implementing plenty of simulation and verification work on NSVP, proved its reliability, expandability and convenience.