Parallel Signal Processing Algorithms Implemented In Hardware

Signal processing is an emerging subject. It relates to two aspects of algorithms and hardware. Hardware implementation of Signal processing algorithm is a bridge to theory and practice, and also science and engineering. A lot of practical applications requires increasing ability of calculation and the real-time processing. Parallel processing theory has been attached great importance to signal processing engineering practice. It can be a great solution to some algorithm that depends on the hardware computing capability, as well as real-time signal processing requirements.In this thesis, signal processing algorithms in parallel hardware implementation of the practical requirements of starting and building a complete set of intermediate frequency signal includes a sample plate to the back-end of the 4 TS201 DSP board high-speed parallel signal processing hardware system, which based on the discusses the theory of parallel algorithms and the specific implementation methods, and to have wide representation and practical engineering significance of the fast Fourier transform algorithm as an example, the implementation of two different parallel algorithms.Initially, this thesis introduces the intermediate frequency sampling technique. The Band pass sampling theories are analyzed. The key performance indicators of ADC sampling device are presented. PCB board of the sampling system is designed and the Electromagnetic Compatibility Design Method of the high-speed PCB designs is discussed. Finally, the FPGA implementation results of the sampling board are given.Second, high-speed parallel signal processing DSP system solutions are studied. A composite coupling structure of multi-processor system architecture is presented form the actual requirement of parallel computing. A shared-bus FPGA design with a bus arbitration mechanism and a SDRAM controller are implemented for the data link between the signal processing board and the signal sampling board.Then studied the basic concepts of the basic methods of parallelization for traditional serial algorithm. Followed by the introduction of fast Fourier transform algorithm principle, this thesis gives an analysis of the internal serial and parallel property of the FFT algorithm. Based on the analysis above, a pipeline block-distribute algorithm and a parallel frequency extraction algorithm are put forward followed with algorithm optimize according to the hardware structure.Finally, this thesis set up a test platform for the actual testing of the two parallel FFT algorithms for computing performance. Then, analysis and comparison of two kinds of parallel algorithm of the characteristics and performance are presented and propose advantages and disadvantages of two algorithms to specific occasions.