Digital Video Broadcasting System For Reconfigurable Ldpc Decoder,

By analizing and rearranging decoding step of soft-decision iterating decoding algorithm based on beliefe-propagation, this paper proposed a modified iteration decoding algorithm. In this modified algorithm, two kinds of messages were compressed to save memory capacitance; some complicated functions were simplified to make implementation easy. The FPGA test proves that this modified algorithm's performance loses are acceptable.Based on this modified algorithm, a reconfigurable QC-LDPC codes decoder architecture was propoased. A log-barral shifter was introduced to passing messages to make interconnection simple; by introducing the SIMD architecture and the idea of micro-instruction, decoding procedure was abstracted as a set of some user-defined instructions, and the code rate and regularity of LDPC codes could be reconfigured any time.This paper proposed a 2-mode reconfigurable QC-LDPC codes decoder VLSI implememtation for DVB-S2 and DTMB system. Synthesized results shows that this decoder has a good balance between the decoding performance and its hardware costs, and is very suitable for multi-mode digital video broadcasting receiver systems...