Research On High-performance Forward Error Correction Code (FEC) Decoding Algorithm And Its VLSI Implementation In Digital Communication Systems

Since the last century, information theory, communication and semiconductor technology have been a pervading and effective technology for the economic activities of human beings, and changing the way that we are living in. Error correction method, i.e. channel coding technology, plays a key role for reliable and high-speed digital transmission. Due to short decoding latency, forward error correction (FEC) is preferable in digital communications, and thus high performance VLSI circuit design are of great research interest.Among the FEC methods, low-density parity-check (LDPC) codes and Reed-Solomon (RS) codes are two linear block codes that are applied to many digital systems. So far, LDPC codes have been adopted in DVB-S2, DTMB, CMMB, WLAN, WiMAX, 10GBase-T, and WPAN; and RS codes have been adopted in CMMB, DVB-T, ISDB-T, ATSC and DVB-C. This dissertation will be concentrated in FEC decoder chip design for the above two codes.The design targets of different LDPC codes decoders depend on the specifications of different systems. The common target is the optimization of error correction performance and energy consumption. The uncommon target comes from the constraint of area and data throughput, and the flexibility requirement. The RS decoder design faces similar questions. This dissertation will study the LDPC and RS decoder design method for several applications with optimized chip area, and power consumption, and with improved flexibility and throughput.Based on optimized decoding algorithm, appropriate parallelism and memory deployment, pipelining, early stopping, low-power and area optimization method, this dissertation designs an RS-LDPC decoder for lOGbase-T applications, a QC-LDPC decoder for WiMAX and WLAN applications, an HS-LDPC decoder for CMMB applications, and a flexible and low-cost RS decoder for multi-standard digital video broadcasting applications.