Chaotic Deformation Of The Des Algorithm Fpga Design And Implementation

With the development of information technology and the prevalence of computer network, information security is a key problem. In consideration of the deficiency of traditional cryptology and the ceaseless improved ability of cryptanalysis, data encryption based on chaos has became a focus of research and may be a new prospective approach in the future. As the representative of tradition block encryption algorithm, DES has a deadly weakness that is too small key space to prevent exhaust attacks. To aim at the problem that the key space of DES is too small to prevent exhaust attacks, an expanding key space method is proposed and a chaotic transformed DES algorithm is constructed. The expanding key space method is based on 3 principles of the Shannon's idea "one-time pad", "infinite key space" and a chaotic system, which can make up of a determinate random number generator. Tangent-Delay Ellipse Reflecting Cavity map System (TD-ERCS) has been proved to have good cryptographic properties by theoretic research and tests. Using the characteristic of the better security Chaos Pseudo-Random Sequence (CPRS) produced by TD-ERCS , the key space of DES increases from 2⁵⁶ to 2¹⁶⁰ and a chaotic transformed DES algorithm such as "one-time pad" is constructed, improving the ability of prevention exhaust attacks extremely.Considering the specific structure of the FPGA , according to the top-to-bottom design method ,the FPGA implementation of such chaotic transformed DES algorithm is presented using VHDL,fulfilling the software simulation and hardware debugging; The whole and module design is detailedly discussed especially the design of data distributor and DES units; The system is enabled to be embedded in existing cryptographic equipments by adding an UART module.