The Research And FPGA Implement Of Data Encryption Algorithm Based On Chaos

With the development of information technology and the prevalence of computer network, information security is a key problem. In consideration of the deficiency of traditional cryptology and the ceaseless improved ability of cryptanalysis, data encryption based on chaos has became a focus of research and may be a new prospective approach in the future. The data encryption algorithm based on chaos and its FPGA implement are mainly discussed in this dissertation. In the part of designing sequence cipher based on chaos, the design for CPRBS generator based on Logistic mapping and LFSR is discussed in great detail, then the sequence cipher algorithm described in VHDL is introduced. The encryption/decryption speed attains 836Mbit/s and the algoritm passes the verification of FIPS 140-2 security requirements. In the part of FPGA implement of DES and its improvement based on chaos, the design for DES implemented in FPGA is emphasized, including the design of operation module, sub-key generator module and control module. For the deficiency of key and the feature of DES algorithm, an improved method is presented based on Kolmogorov flows mapping and the key of enhanced algorithm increases from 56 bits to 136 bits, while the reliability of DES is remained. Finally, the parallel interface in EPP mode is designed and the whole data encryption system designing between FPGA and PC is given to carry out the verification of data encryption results.