Research And Implementation, Based On The Detection Of The If Digital Platforms Pretreatment

In recent years, there has been attractive development in software radio, which draws much attention since 1992 when it was proposed. Its fundamental principle is to make ADC close to RF antenna as much as possible. However, due to the limitation of devices, it is difficult to implement the immediate sampling of RF signals. Generally the analog signal is digitized at intermediate frequency (IF) and various digital signals are accomplished at baseband after digital down conversion.This design is based on an intermediate frequency digital collecting platform which has the characters such as embedded digital signal processing algorithm, hardware and software reconstruction and so on. It focuses on the envelop detection of modulated intermediate frequency pulses after digitization and the change of sample rate to the intermediate frequency signals by digital frequency conversion algorithm to ensure the real-time signal process of rear circuits.This thesis discusses the conventional scheme of IF digital detection--digital quadrature demodulation and its application. The problems in the practical application are analyzed. These problems are such as low processing speed, high resources occupancy rate etc. So another envelop demodulation scheme without multiplicative structure--absolute values demodulation is selected in the design. The simulation waveform is given after the analysis of the digital down conversion of absolute values demodulation. Lays emphasis on CIC decimation filter based on novel CIC detection scheme, and illustrates the influence of CIC filter order and stage on its performance. Then a demodulation system is designed base on the absolute value method. It contains five stages, with decimation factor of 8. When the maximum input data rate is 250MSa/s and the alias rejection is approximately 100dB, the maximum input bandwidth is approximately 3.125MHz and the pass-band attenuation is approximately 1.62dB. We use FPGA to implement the scheme based on means of absolute values, and present hardware simulation waveform. The feasibility and the efficiency of this scheme are demonstrated as well.