Performance Of The Mdapsk Modem Technology And Fpga Implementation

In order to transmit data efficiently, multilevel modulation techniques are widely used in communication system under limited bandwidth. This dissertation mainly studies the algorithm and implementation of multilevel differential amplitude and phase keying (MDAPSK). Compared with the conventional quadrature amplitude modulation (QAM), differential demodulation of MDAPSK reduces the complexity in the receiver, requires no training sequence of symbol at the expense of degrading the bit error rate (BER) performace.In this thesis, the fundamental theory of MDAPSK modulation and demodulation is introduced, and the derivation of algorithm is also completed, based on which the basic structure of modulation and demodulation system is designed. This paper explained the process of realization in detail for MDAPSK modulation and demodulation with M=16, 32 and 64. Their bandwidth efficiencies and BERs in the additive white Gaussian noise (AWGN) channel are analysed through simulation results in Matlab. The BER performace of simplified algorithm based on both arithmetic and geometric mean thresholds is compared with the conventional algorithm.Through the profound understanding and study of MDAPSK modulation and demodulation, the 16DAPSK is chosen to design a circuit and verified on field programmable gate array (FPGA). Firstly, this paper proposed a specific circuit design scheme that respective sub-module is devised in patition with the top-down method. Through the analysis of their logic circuits, the RTL code is programmed and verified for the function and timming. Secondly, both pulse shaping filter and bit synchronization modules are explained for the design principle and implementation in detail. Then all the individual modules composed a whole system to test for ensuring the stable performance. At last, the designed hardware platform based on FPGA chip is presented in the paper, and the circuit installation and debug are completed.In this dissertation, a test scheme is also planned. When downloading the compiled program to the FPGA chip, through recording and analysing the waveform, the modulation and demodulation system of 16DAPSK can run correctly and realize the goal of implementing the digital signal transmission at 1Mbps bit rate and 2MHz carrier frequency.