H.264 Encoder Optimization Based On Dm642 And Design

H.264 based on the H.263 and MPEG4 video coding standard is the latest Video Coding Standards published by jointly ITU-T (International Telecommunication Union) and ISO (International Organization for Standardization). Compared to earlier standards, H.264 adopts some new technologies. The new method is more convenient, safer, not easy to be forgotten and not easy to be replaced. It can be widely applied in "conversational" (video telephony, mobile video communication) and "non-conversational"(storage,broadcast,streaming) applications. The research and implementation of H.264 real-time coding technologies is one of the hot research topics in the area of image communication.Using high-performance digital signal processor to achieve real-time H.264 encoder is a rapid and effective method. It's better to the rapid popularization the application of H.264 video codec standard. The TMS320DM642 device is a fixed-point digital signal processor (DSPS) based on the second generation high-performance very long instruction word (VLIW) VelociT1.2 developed by Texas Instruments (TI). It extended instruction set for a special video/image processing, enhanced video processing parallelism. At a clock rate of 600MHZ, the DM642 device can perform up to 4800 million instructions per second (MIPS). The DM642 Digital Media Processor has a number of Peripheral Interface Chip, it is suitable for the video and imaging applications, for example, the audio/video transmission and security monitor over IP and wireless networks.Firstly, the paper introduces the purpose,the current situation and the challenges of the topic, then introduces how to develop and optimize the H.264 "baseline" encoder ported from VC platform on the hardware platform based on TMS320DM642. The source program is the encoder part of the "x264" which is one of the open H.264 codec software. For the implementation of H.264 video encoder based on DSP, we should consider the characters of DSP, except for characters of video encoding algorithm. The paper is to improve the kernel algorithm efficiency of the encoder using linear assembly language and assembly language which can improve the parallelism inherent in the H.264 encoder. The optimization of the kernel algorithm included intra-prediction encoding, Integer DCT and Quantization . Considering the character of two level Cache structure of DM642 chip, a cache optimization strategy is proposed to realize the real-time video application system. In the end, the paper introduces the implementation of H.264 real-time video encoder.Our H.264 encoder can encode real-time for QCIF resolution video, 12-18 frames per second (fps) for CIF resolution video. The decoded video picture provides high subjective and objective quality.