Low Spurious,Low-noise Phase-locked Double-frequency Signal Source Design

In recent years,the development of electronic technology is getting faster and faster,electronic products are constantly being introduced,and people are increasingly relying on electronic products and signal sources,which are called the "heart" of electronic systems.They provide clock signals for electronic systems.Signal sources are widely used in various fields such as communications and missiles.High-performance high-frequency oscillators often have difficulties in direct manufacturing because of process and technology limitations,and they have high costs.The use of frequency synthesis technology can quickly create a suitable signal source,save time and reduce costs,which promotes the frequency synthesis technology in the electronic system industry has been widely used and developed.The content of this paper is to design a 100 M signal source using phase-locked frequency multiplication technology.The thesis takes the development of PLL technology as the entry point.Firstly,the basic theory and structure of the phase-locked loop are introduced.Each component module is analyzed and modeled,and each important index of the signal source is introduced.Then by analyzing the types of noise and noise of the signal source and establishing the noise model of each component,some opinions and methods for improving the key indicators are proposed.The research topic of this dissertation uses two kinds of schemes.Firstly,the frequency source is designed based on phase-locked loop chip of integrated phase detector,VCO and frequency divider.This program is based on the ADF4351 phase-locked loop chip,simulated by ADIsimPL software and used as a reference,and then combined with MATLAB to calculate the value of each device of the loop filter to design a suitable loop filter and design the peripheral circuit of the chip.The system uses STM32 as the master chip to control each register of the PLL chip to design a complete signal source system.In order to improve the various functions in the integrated chip,especially the VCO,better performance indicators are obtained.Proposed and designed the second plan.This scheme uses a discrete diode balance phase detector,voltage controlled oscillator,and frequency divider to build a phase-locked loop circuit and compares it with scenario one.Finally,using R&S FSUP 8 signal source analyzer to test and verify the performance indicators of the two schemes,the test results show that scheme 2 improves over 10 dBc in terms of spurious simulation,and the phase noise in the near end improves compared with scheme 1 above-22dBc/Hz.The phase II noise test result of scheme two reaches-102dBc/Hz@10Hz,-130dBc/Hz@100Hz.In summary,the spurious pseudo-system and phase noise indicators have been significantly improved,and have reached the required design indicators.