Confidential Communication Rs Codec Fpga Implementation

It will produce error codes when the digital signals are transferred in the channel with interference. The error-control coding is usually adopted to correct the errors produced in the process of transfer, in order to ensure the realiability and validity of communication. The purpose of this thesis is to research how to enchance the reliability and validity of communication by error-control coding with a focus on one kind of channel codec arithmetic and its logic realiziation ways on hardware. The code stream has been transferred on the FPGA hardware for the purpose of performance test. On the basis of the above research, this thesis extended the fields of the study trasnsversely, including the FPGA realiziation and high-speed digital circuit.Error-control coding is an effective method to enhance the communication quality by adding redundant information after the original message. As a typical error-correcting code, RS code possesses the most strong error-control ability among the linear block code and can correct the random errors and burst errors. It is widely used in deep space communication, cellular communication and DVB system as it can correct the random errors and burst errors. With the improvement of RS arithmetic and the development of the hardware, the practical application of RS coding will getting more abroadly.In the course of research, I analyzed the problem and focused on the important and difficulty ones. After the implementation of respective module, I composed the individual module as a whole system and adjust the system for stable performance. In the EDA design, this thesis took the top-down method, imlplemented the individual module with RTL coding and time-order simulation, and finally instance the component in the top level accurately.First, this thesis introduced the background of digital communication. Then put forward the error-control scheme, discussed the arithmetic of RS(31,15) coding and its logic circuit, and RTL coding with logic simulation and post-fitting simulation. Meanwhile this thesis discussed the general design ways of the FPGA and high-speed digital circuit. Finally I designed the hardware platform based on FPGA, and tested the hardware with code stream.Through the profound understanding of RS coding, I described the RS arithmetic with verilog HDL and implemented the RS arithmetic on Altera's Cyclone series FPGA. The maxim frequency of the coding is up to 158MHz, and the decoding is 91MHz. The hardware system passed the test at the frequency of 30MHz.