Study Of The Noc Bus Coding Techniques

Deep sub-micro (DSM) processes present many challenges to Very Large Scale Integration (VLSI) designers, and on-chip communication has become a major performance bottleneck of system-on-chip (SoC). With shrinking feature size, scaling of supply voltage, increasing interconnect density and faster clock rates, global on-chip communication suffers from following three major issues: high power consumption due to both parasitic and coupling capacitance, large propagation delay due to capacitive crosstalk, and increased susceptibility to errors due to deep sub-micron(DSM) noise. Future SoCs will follow the network-on-chip (NoC) paradigm, where energy-efficient, high-speed and reliable communication between various SoC components is vital, and NoC bus designers must take the three problems above into account.As for the deep sub-micron bus based on-chip communication, current research work mainly focuses on bus encoding techniques. By adding some redundant information, bus encoding can eliminate crosstalk well, and also provide some error control features to combat noise. Begins with NoC-based bus encoding techniques, this thesis shows our researches on the following three aspects:Firstly, discussed some features of deep sub-micron buses, model of power consumption, delay and reliability. Then, analyzed the existing bus encoding techniques (such as low power coding, crosstalk avoidance coding and error control coding), which lay a foundation for future bus coding schemes.Secondly, in order to address the three problems simultaneously, this thesis proposed a new compressive coding scheme SEC-DAED-SDAEC+DAP, which joints unequal error protection code and crosstalk avoidance code based on the united coding framework. According to packet format of NoC, the proposed coding scheme provides unequal error protection abilities for different parts of the packet, wherein routing information in header part has much more ability for error correction. And this coding scheme has crosstalk avoidance feature to reduce delay, too. When applied to a 10-mm 32-bit parallel bus in SMIC 0.13um CMOS technology without any loss in reliability, the simulation results show that the proposed scheme has 38.25% power consumption improvement and a 1.589 speed-up over the uncoded bus.Thirdly, in packet-switching based NoC, current coding schemes mainly aim at overall coding based design mode. In order to get the routing information, needding to decode the received packet integerally in router node, which make routing path influence the overall power consumption and delay of on-chip communication very much. Taking packet format of NoC into account, this thesis applied a hybrid coding design mode which based on partial coding for header packet. Based on the hybrid coding design mode, this thesis then proposed a joint coding scheme HC-Triple-Hsiao-Dup. As manifested by the simulation results, HC-Triple-Hsiao-Dup has much better improvement trend in aspects of speed-up, energy-saving and area-overhead over other coding schemes which based on overall coding design mode. When the average hops are 4, HC-Triple-Hsiao-Dup achieves 1.7 speed-up and 42% energy-saving over the uncoded bus.