The Design Of FEC Code In Short Range Communication

With the advent of the digital era of intelligent, short-range wireless communications technology is developing rapidly, and reliability of data transmission error control technology is required to ensure that, so the research for short-range wireless communications error control technology has important practical significance.The problem with lab scenarios GFSK baseband chip designed based on a short-range wireless communications for FEC codec module. This thesis analyzes the error control technology developments, GFSK baseband chip scenarios characteristics, existing FEC classification, convolution code base, designed to determine the thesis GFSK baseband chip FEC codec implementations. On this basis, the thesis gives a GFSK baseband chip FEC codec module specific architecture, and one of the key circuit module includes butterflies, remaining route management unit, the branch metering unit were optimized RTL design and implementation. As used herein, Verilog language completed FEC codec module design and build FPGA platform evaluation. Verification and test results show that, FEC module is working properly; decoding circuit size less than 1K logic unit; module system clock maximum 75MHz; decoder input SNR is 9dB, the error rate is less than 0.1%, to meet design specifications.This thesis solves the laboratory GFSK baseband chip error control problems and meet the needs of chip application scenarios. It has broad application prospects in the short-range wireless communication.