Terrestrial Digital Tv Integration Design And Implementation Of The Program The Receiver Synchronization System

The FPGA-based hardware implementation and design of the receiver's synchronization system of the merged blue print for digital terrestrial television broadcasting in china has been completed in this project. The main hardware-platform is based on the Altera's Stratix series FPGA chip EP1S80F1020C5. The realizations of the digital down converter (DDC), matching filter and all the system synchronization have been implemented based on FPGA. In this dissertation, the developing status of DTV, which is followed by the whole structure introduction of the transmitter and system summary of the receiver of the merged blue print, is introduced firstly. The design of base band converter, which is composed of digital down converter and matching filter, is introduced importantly in chapter 3. In chapter 4, the arithmetic analysis and architecture design of the synchronization system of the receiver are introduced in detail. The timing domain synchronization including symbol, sampling and frequency synchronization is discussed according to the characteristics of frame structure in merged blue print. At the same time, this dissertation has raised the process of the phase matching in the mode of changed PN. The chapter 5 simply introduces the theory and hardware design of the residual frequency estimation and revision. The academic simulation is also well done in this chapter. The debugging results on the PCB of the front system of the receiver are described in chapter 6. What I have mainly done in the project is listed as follows:1. Read papers associated with the project and get familiar with system.2. Establish the transmitter and channel model for the receiver simulation.3. Complete the arithmetic design and simulation of the DDC, matching filter, symbol, sampling and frequency synchronization.4. Complete the arithmetic design and hardware code of the residual frequency estimation and revision.5. Complete the function simulation, analysis and validation of the whole front system of the receiver in the merged blue print system.6. Complete the debugging on the PCB of the system synchronization.