An Lsi Testing Method

A compilation/generation method for test program of large scale integrated circuit (LSI), called Fault Simulation Method is presented in this paper. With the development of large scale integrated circuit, the number of input/output pins for a single circuit are increasing, which results in an exponential rise in the test vector. With regards to the test time and cost, the traditional exhaustion method can no longer compile and generate a test program for large scale integrated circuit which can meet the requirements. Compared with the traditional method, the new method can ensure the test vector within an acceptable scope, while the accuracy and reliability of test results are still maintained simultaneously.The effectiveness of this method is verified theoretically and practically, and it is also introduced how to compile the test program of large scale integrated circuit by using the fault simulation method from the aspects of hardware and software. In this paper, the concept of random sampling verification is introduced into the area of large scale integrated circuit, which solves the problem how to calculate the fault rate of compiled test program, and can be a strong technical support for the accuracy and effectiveness of test results of the compiled test program.Through the comparison with other compilation method of test program for large scale integrated circuit and the verification of test results, the author thinks that the fault simulation method is a suitable compilation method of test program for large scale integrated circuit in the present phase in China.