Digital Audio Wireless Transmission Platform

An algorithm of FEC (Forward Error Correction) system and it's FPGA implementation were researched,. Then the FEC system was applied to an audio transmission platform.The platform can decrease the error bit rate to 1×10-7 when channel error bit rate is 3×10-3. VerilogHDL was chosen to design the circuits. The IP core's synthesis, place&route were based on develop tool QuartusII4.2. The timing simulation was based on Modelsim. At last, the IP was downloaded to Altera's FPGA for real-time simulation and test.Firstly, the scheme and architecture of the FEC system, the module dividing, the design method and the coding style were introduced. After that, the thesis gave out the detail of each module as well as the testing data, the implementing results and the timing simulation waveform. And it gave a detailed description of the downloading and verification on hardware.At last the FEC system was applied in an audio transmission platform,which gave a good example for how to use the FEC system. While designing the system, we spent a lot of time on considering how to divide and define each module and how to coordinate and interconnect these modules. We followed the top-down method to design. As for the interconnection of each module, we defined the interface signal to communicate between them, and the internal timing of the module was control1ed by states machine. When constructing the code, we pay much attention to hardware resource and concurrent executable ability of the Verilog Language to make the design close to the hardware working way, so we could get a high speed with a low hardware cost to satisfy the demand, performance and practicability. It also gave out some reference for the future SOC.The FEC system can increase the error-correcting ability if we increase the iterative times,which express the excellence of Top-Down designing and blocking.