Digital Circuit Delay Testability Design Study,

Higher reliability and increasing performance requirements show the need not only to guarantee functional correctness of digital circuits, but also to operate these circuits at their highest speeds correctly. Delay testing is a key technique to guarantee the temporal behavior correctness and thus draws much attention. The thesis is concentrated on delay testing and testable design of combinational circuits. First, the thesis analyzes the delay fault testability of ETG PLA, which is a kind of two-level circuit with test generation complexity being linear to the number of products. Based on the properties of ETG PLA and sufficient conditions for gate delay faults to be robust or VNR testable, we prove that each gate delay fault of ETG PLA is robust or VNR testable, and its test vector pair is easy to generate. However, it is found that there are untestable path delay faults in ETG PLA under path delay fault model. Recently published results have also shown that, for many circuits, a large percentage of path delay faults is neither robust nor VNR testable and these faults may affect the normal response of these circuits. Design for testability is a useful technique to improve testability of circuits and thus to enhance reliability of the circuits. Then the thesis discusses the design for delay verifiability of combinational circuits, which is a kind of design for testability, since delay verifiability is enough to satisfy the requirements of temporal correctness of combinational circuits. A new design of delay verifiable two-level circuits by adding extra inputs is proposed, and a synthesis algorithm is given in the thesis. Experimental results show that the hardware overhead is about 3.4% on an average,...