Research On Design For Testability Based On The Framework Of SOC

The subject of this dissertation is the research on the design for testability in the design environment of System on a Chip. The original test methods mostly used the functional test vectors to test the integrated circuits. In the current, the design for testability (DFT) techniques have been one of the necessary methods to design the more and more complex Very Large Scale Integrated circuits with the deep sub-micro meter technology. This dissertation is aimed at a novel DFT solution, which can fix the new problems coming with the development of the design and fabrication techniques.The scan-based DFT technique is the base point of the work in this dissertation, because of its outstanding advantages, such as high fault coverage, standardized architecture, low complexity of test generation, high efficiency of the test vectors and so on. The Scan-based DFT technique is the most popular DFT technique.The power dissipation is one of the critical facts which should be considered carefully when designing the SOC. Further more, the mechanism of testing forces much more switching activities in the testing mode than that in the normal working mode. So the DFT method with low testing power character has been the hotspot of the research on DFT。At the same time, the testing time is still one of the most important optimization facts for the scan-based DFT techniques because of its inherent serial manner.In this dissertation, a set of DFT solutions, from the design of internal architecture to the external data compression, are proposed to meet the requirements for the testing power and the testing time. First, the low testing power DFT solution -- Scan Array architecture are presented. In the Scan Array, the inserted wrapper and paralleled leaf scan chain reduce the testing power as low as the power dissipation in the normal working mode. Scan Array can also benefit the design of multiple clock domains and the optimization of connectivity.Pseudo build-in self test is one auxiliary method based on Scan Array to shorten the testing time and decrease the testing data volume. It makes fully use of the architecture of Scan Array to generate the test vectors randomly. The random test vectors are used to detect one part of the fault set. So less external test vectors are demanded and less testing time is needed to transfer the data.SAC compression algorithm is also presented in this dissertation, which can compress the external test data with stable compression rate. The testing time and testing data can even be reduced when implementing SAC with Scan Array and PBIST. A lot of theoretic analysis and experiment results show their outstanding performance in the optimization of testing power, testing data volume and testing time.