Based On Multi-chip Adsp-ts201s Parallel Radar Signal Processor Design And Realization

The Parallel Signal Processing Technology is an emerging technology that can be applied in the modern radar and communication systems, it can offer powerful signal processing capability to many applications, especially in Radar signal processing. Using a high-parallelized, reconstructurable architecture, we can connect many high performance signal processors together to be a high performance signal processing system. The architecture of the system and the configuration of resource can be reconfigured according the need of the algorithms. This thesis is focused on the study of the signal processing system based on ADSP-TS201S on hardware design, hardware debugging and software design. The significant results of the work include:1. With deep understanding of the hardware and software of the original DBF weight processor, a lot of work has done on the debugging of the interface of it, and now all the interfaces run perfectly.2. Based on the architecture of the DBF weight processor, compared with some other high performance parallel signal processing architectures, a parallel architecture specially for the LFM Radar was proposed, which can make the most use of the hardware resource and more efficient.3. Use the Xilinx ISE developing tool and ADI VisualDSP++ developing tool to develop the configuration the resource and timing. The source data distribution and the result assembling have been realized, so the whole signal path of the signal path has been finished.