GPON FEC Codec Research And Implementation

Forward Error Correction(FEC) has been widely used in the modern communication system. FEC is adopted in Gigabit Passive Optical Network(GPON). FEC in the GPON can reduce the error ratio at the receiver and increase the reliability of communication. At the same time, FEC can decrease the requisition for the performance of the optical devices.FEC in the GPON adopts the Reed-Solomon(RS) code. This paper emphasizes on the most popular RS decoding algorithm: Berlekamp–Massey algorithm and Euclidean algorithm, and their improved form. This paper utilizes the VLSI design method to map the algorithms to the hardware architecture, and has realized the RS encoder and three kinds of RS decoders.In this paper, a new architecture of hardware decoder based on the Modified Euclidean Algorithm(MEA) is provided, and it is called the FPrME (Fully-pipelined recursive modified Euclidean)decoder. It's critical path delay is very little, and it operates in the fully-pipelined continuous decoding manner. Compared to the Altera's newest IP Core, the FPrME decoder is better in either size or rate. The encoder and decoders in the paper has been tested on the circuit board using the Altera's FPGA of Stratix GX EP1SGX25DF672C7 with the system clock of 125MHz.Based on the realization of the encoder/decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel FEC circuit and scrambler complying with the protocols and maken a simulation.The FPrME decoder is advanced in the world. The parallel FEC circuit completely conforms to the ITU-T protocols ,and has important practical value.