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High-performance Router 10g Ethernet Line Interface Technology Research,

Posted on:2006-06-04Degree:MasterType:Thesis
Country:ChinaCandidate:Y Z ZhaoFull Text:PDF
GTID:2208360182960408Subject:Military communications science
Abstract/Summary:PDF Full Text Request
With the maturation of the standard in 10Gbps Ethernet line interface and the rapid popularization of this technology, the 10G Ethernet line interface is becoming an indispensable line interface in design of a Terabit high-performance router. According to the research of the National 863 important Program Plan "The basic platform and experiment system for terabit scalable high performance IPv4/v6 routers", this thesis deeply analyzed and researched the difficulty in design and key technology in implementation of the 10G Ethernet line interface. Based on the FPGA technology, at last this thesis designed a 10G Ethernet line interface which can satisfy the performance requirements by put forward an 1 OGbps line interface full pipeline support architecture and a strategy in efficient management of bulky data table, and passed the elementary test.Summarize this thesis; the details are list as below:1. Analyzed the difficulty in implementation in high speed data processing under the layer 3 in 10Gbps speed and efficient management of bulky data table;2. Put forward a data processing full pipeline support architecture base on FPGA by mark up the input data processing pipeline and the output data processing pipeline;3. Designed and realized a high speed table lookup pipeline by "FPGA+TCAM+SRAM" to satisfy the 10Gbps line speed lookup of the 40 bytes packet length , this pipeline design can implement lookup speed at 100 million searches per second.4. Established an entrance buffer demand analysis model for the high speed lookup pipeline, analyzed the biggest entrance buffer demand and the average entrance buffer demand of the high speed lookup pipeline, provide a theory basis to the buffer demand set in FPGA program design;5. Designed and implement a strategy to implement efficient management of bulky data table based on the hash table.At last this thesis designed a debugging plan for the 10G Ethernet line interface card; this plan has an important practical value in the terabit high performance router's road to industry.
Keywords/Search Tags:high performance router, 10G Ethernet, line interface card, FPGA
PDF Full Text Request
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