A Study Of Design And Implementation Technologies Of The ATM Interface For The High-Performance IPv6 Router

As designed for the next generation network, the high-performance IPv6 Router must support multiple network protocols.The ATM interface is one of necessary interfaces supported by the IPv6 Router.Based on the research of ATM protocol and the principle of "IP over ATM", the hardware-implemented scheme for the ATM interface is proposed in this thesis.In this scheme, universal scheduling strategies and a buffer management of AAL5 are proposed. To resolve the problem of calculating arithmetical compliment of the number which isn't 2n in VHDL, a mechanism of segment recursion look up is proposed. And a mechanism of parallel multiple queues schedule is proposed to solve the low robin efficiency of multiple queues.Functional modules and key chips of the whole hardware system are given, and we adopt a no-matching route by simulating with ICX to accomplish the design of high-speed PCB. Furthermore, the analysis and implementation of pivotal units of input-output link control circuit are presented in detail. The results of performance test indicate that this ATM interface board runs all right and and satisfies all performance requirements.The main contributions and innovations of this thesis include: Based on functional requirements of the interface and principles of the AAL5 protocol, the design of the hardware system for the ATM interface and its modules compartmentalization are proposed. Consequently a hardware implementation scheme of the whole system and all modules are proposed. Furthermore, the key implemental methods are presented in detail. In the design of AAL5, to satisfy the equity and requirements for packet processing, novel scheduling policies of cell round-robin (CRR) and packet round-robin (PRR) are used together. And to improve throughput and reduce packet-loss rate of system, a novel scheduling policy, named threshold based scheduling policy (TBSP), is presented. A buffer management scheme, named classification based random early detection (CBRED), is proposed with TBSP to guarantee the delay and QoS requirements of real-time traffic. A mechanism of segment recursion look up is proposed. In this mechanism, the scheduler judges the next queue needed being read when the current queue is being read. So there is no waiting time in the multiple queues switching. This mechanism is stable working and can deal with burst traffic. A universal mechanism of segment recursion look up is proposed to resolve calculate arithmetical compliment of the number which isn't 2n. Based on the facility of 2ndivision in VHDL, divisor is divided into segment, combined with recursion look up, so we can work out the result firstly and exactly. The engineering-simplified design of SRLU is implemented in the ATM interface.