The Design And Realization Of High Density G Bit Ethernet PL4 Interface System

In the present high density Ethernet controller chip, almost all the commercial chips adopted the POS-PHY Level 4 (PL4 ) interface agreement in their systematic sides. This text on the basis of studying agreement standard of this interface , carry on research to high density G bit Ethernet circuit interface detailed conditions that function require, support chain layers of PL4 standard receiving and dispatching end design plan of interface mainly, and has carried on detailed analysis and exposition with realizing technology to the design of the hardware system. The main work of this paper is as follows:1. A new algorithm of Diagonal Interleaved Parity is developed for the data with bit-width configurable, which can be realized in FPGA, so the realization of POS-PHY Level 4 in FPGA is resolved.2. Through setting up models of lining up of the G bit Ethernet circuit interface of high density, analyze PL4 interface receive and dispatch end line up model buffer memory capacity demand and deployment tactics of deployment machine of formation, to carry on comparative analysis on the basis of deployment to divide into block on the basis of deployment that divide into groups.3. To guarantee the fairly sharing of the bandwidth between all interfaces, the schedule policy Deficit Weighted Round Robin (DWRR) which is based on packets is adopted in the PL4 interface received link control circuit; To improve the using efficiency of buffers and decrease the ratio of packet lost, the schedule policy Combined Bidirectional Queue Threshold Round Robin which is based on chips is adopted in the PL4 interface sent link control circuit.4. By analyzing the realization of scheduler, a kind of scheduler designed with masker and Priority encoder is given and the efficient of scheduler is increased.5. By the implementation of POS-PHY Level 4 in FPGA, the reliable high-speed transition of multi-channel between a MAC layer device and a logic link control layer device is realized.