Vlsi Implementation Of The Java Processor

The property "Write once, compile anywhere" lets Java become a very popular programming language on internet. Java is platform-independent, object-oriented, multi-thread supported and safe, so it is applied to some small, low-power embedded consumer electronics. Java has to use virtual-machine techniques to be "platform-independent", which causes the slow running speed on some universal processor. The software design method is slow and occupies much resource of internal memory. However, implementing Java in hardware can make up the drawbacks of software design.This thesis designs a four-stage pipelined Java hardware accelerator. It can execute most of the Java Virtual Machine (JVM), it can run as a single processing unit in an embedded system or FPGA. The essence of the accelerator is to substitute the Java bytecode translator for accelerating chip. At the same time, there is a good balance between speed, area and power. The accelerator is transparent to any operation system. There is no need to increase the system frequency, to add additional memory and tools. It supports UART interface and WISHBONE bus so that it can communicate with any baseband processor, SoC or embedded microprocessor.This thesis is devided into three parts. The first part introduces the JVM, the second part explains the detail hardware design of the Java accelerator, the third part gives the simulation and synthesis result. At last we discuss the subsequent work. The design of the instruction set depends on different usage frequency and different realization complexity. Most of the simple JVM arithmetic/logic instructions can finish in one or several hardware clock period. The extension of original instruction set envokes the communication with external memory and internal system registers. We also improve the stack architecture and use two-stage pipeline stack. This microprocessor uses dual-port RAM as Java stack memory, which reduces the consumption of memory resource. Thus it can be transplanted to low-cost FPGA devices. Furthermore, we use VHDL to model and simulate processor core and the core has passed functional test. The result of synthesis tools indicates that the processor core occupies less hardware resources and area , and the frequency is higher.