Ip Core Development Standards And The Bus Protocol Converter Ip Core Design

With the rapid development of the design technique of the integrated circuit and semiconductor manufacturing technology, System on a chip design becomes feasible, which means the arrival of SoC era. The cpu, memory , I/O interface and other modules can be integrated on a single chip that can realize the whole system function. As we know, Gordon Moore made his famous observation in 1965, just four years after the first planar integrated circuit was discovered. Moore observed an exponential growth in the number of transistors per integrated circuit and predicted that this trend would continue. Moore's Law, the doubling of transistors every couple of years, has been maintained, and still holds true today and will continue at least through the end of this decade .And based on the Dataquest company investigation, the IC manufacture ability increases by 58% every year, but the IC design ability only increases by 21% every year. So how to meet the gap is a serious problem. We know, reuse of IP core is the SoC's foundation. Intelligence Property Core, is the designed and verified module, that can realize the special function. We may put IP core reuse like this: during the process of SoC design, we are able to inherit, share, or purchase IP cores we need, so that we can use EDA tools to design, synthesis and verify them. Reusing the IP core can improve the system design efficiency and thus make new products available on market much faster. So we can obtain better market competitiveness. However, because the IP core design teams come from different research fields, or different companies, with knowledge of probably different EDA tools, it becomes moredifficult to integrate them. So IP core standardization is an extremely urgent problem. Already there are some organizations established, such as VSIA (Virtual Socket Interface Alliance). These organizations mission is to establish the IP core's standard which from multiple sources.The work of this paper is to understand and study the development standard of IP core, and based on AHB bus Rev2.0 and PCI bus 2.2 ,and design a IP core about the AHB bus and PCI bus protocol translation. In this thesis, the design was described with VHDL hardware languages , on Max Plus II software platform, and realized the protocol of AHB-PCI bus translation the design of IP core , adopts the top-down design method, including such module as interface of PCI , AHB interface , AHB arbitrating device , AHB address decoder and FIFO ,etc. At last the design has been simulated successfully.