Fpga Implementation Of High-end Traffic Management, Traffic Shaping And Label Processing Algorithms

The enhancement of the overall performance of Internet concernsthe fields of transmission technique, host's speed, operation system,switch, MUX, etc. And the performance of router is still the most pivotaland important factor. Usually, Core router consists of three key parts ofnet processor, switch structure and PHY layer.In order to enhance the performance of Core router, relief thebottleneck of interconnect, improve the data process ability of netprocessor when there is special requirement of traffic management, thissystem adopt ASIC to accomplish the required process of data package.As the interface between the Network Processor and switch fabric, TMP(Traffic Management Processor)has important function to manage thetraffic of network.TMP chip includes two parts of ingress and egress, has the processcapacity of 20G. It joints with the Network Processor by two SPI4.2interfaces of 10G, and the switch side provides a high-speed serialinterface (SerDes). It has the function of the integration of trafficmanagement(TM) and SerDes. This paper describes the designing andrealization of the key parts of the ingress part of TMP chip: ingress queuemodule (INQ) and label processor module (LBP), and the verification ofthe ALTERA's SPI4.2 IPCORE. The INQ module shapes the data from theNetwork Processor, include the data-type distinguishing, error packagefiltering, data buffering and package length stat for one type of the data,etc; the LBP in charge of the distinguish of different type of packages,and to compute the storage queue number of the package in the nextmodule by look up table, and re-construct the header of package.This paper describes the designing and simulation of the trafficshaping and label processor module in TMP chip, and the subsequentverification and test based on FPGA system. The test result indicates thatall the modules reaches the target and realizes the expected functions.