Research On Parallel Packet Switch Technology Based On Universal Network

The progress of routing and switching technology results in the quick development of the internet; On the other hand, the quick development of the internet aslo brings up new requirements and challenges for the research of routing and switching technology: First, the switches and routers should be able to sustain with higher port speed and huger capacity, so as to be adapt with the expansion of the internet and the increasement of the internet traffic; Second, switches and routers should be able to provide with good quality of service, so as to be suitable with the rich and colorful trend of the internet application; Third, they should be able to support multicast, so as to fit with the expansion of multimedia traffic.As a result of the maturity and wide application of optical fibre transmission technology, the link transmission rate makes remarkable progress. In this case, the bottleneck of the internet transmission changes from the data link to the switch node. Subject to the low development speed of memory and chip manufacture and limited by the complexity of scheduling algorithm, the work speed of switches and routers improves slowly. A popular solution of this problem is to construct high-speed parallel switch system by using multiple lower speed switches. The proposal of PPS(parallel packet switch) just coincides with this solution. With the recent research in "the Universal Network Architecture Model and the Switching and Routing Theory and Technology" which is sub-project of the National Basic Research Program of China (973 program) "Fundamental Research on the Architecture of Universal Trustworthy Network and Pervasive Services", our dissertation pays most attention on the study of problems such as how to provide high-speed huge-capacity switch, how to guarantee quality of service, and how to support multicast traffic for parallel packet switch architecture and scheduling algorithm. On the whole, the main work and contributions of this dissertation can be concluded as follows:A distributed parallel packet switch with bufferless demultiplexor and multiplexor (BDMPPS) is proposed. Via introducing VIL(virtual input link) and VOL(virtual output link), BDMPPS can make each traffic flow be load balanced between central planes and be transmitted orderly at output port, on the premise of obeying input link constraint and output link constraint. Simulation results show that the average delay of BDMPPS is lower than popular distributed PPS, and is close to centralized PPS, but the scheduling complexity and communication overhead of BDMPPS is better than that of centralized PPS.A practical distributed parallel packet switch (PDPPS) is proposed whose central plane is based on CIOQ switch. As the cells within each traffic flow may be seriously out of order when they arrive at multiplexor after transmitting through central plane, PDPPS introduces VIQ(virtual input queue) at the output side of each central plane and VOL between central planes and multiplexors by means of research results of BDMPPS. In this way it is equal to moving the required memory from high-speed multiplexor to low-speed output of central plane, so as to reduce the amount of required high-speed memory significantly and improve the feasibility of PDPPS. Simulation results show that the average delay performance of PDPPS is better than that of popular distributed parallel packet switch. As a result of the usage of CIOQ as central plane, the scalability of PDPPS is improved under high-speed environment.In view of the increasement of QoS requirements of current internet traffics and the centralized scheduling problem of CIOQ switch, a CICQ based Diffserv supporting parallel packet switch (CDPPS) is proposed. By making use of CICQ as central plane, CDPPS can make the scheduling scheme of central plane with better scalability. The supporting of DiffServ in CDPPS makes it provide QoS guarantees for different kinds of traffics under the circumstances that the network is becoming bigger and the application kinds are becoming more. Theoretical analysis and simulation results show that CDPPS can provide good fairness and nice delay performance, and can guarantee QoS for different traffic classes under high-speed environment.The same kinds of switches are used as central planes by conventional parallel packet switch. Switches with different kinds of scheduling algorithms, different speedup, and different memory amount, may get different throughput, delay, and lost rate. Based on this idea, a heterogeneous parallel switch architecture (HPSA) is proposed which can guarantee QoS with coarse granularity. By making different kinds of traffic classes be switched by different kinds of central planes, QoS of each traffic class is guaranteed. Simulation results show that the QoS performance of each traffic class in HPSA is better than that in conventional single chip switches and parallel packet switches.A uni- and multicast supported parallel packet switch (UMSPPS) is proposed. By dynamically changing the number of switches that are used to switch unicast traffic and the number of switches that are used to switch multicast traffic, UMSPPS can deal with any mix of uni- and multicast traffic and get ideal throughput and delay performance. Simulation results show that the average delay of UMSPPS is always lower than that of conventional uni- and multicast scheduling scheme.The requirements of switch system, which can provide high-speed huge-capacity and pervasive services for the project "Fundamental Research on the Architecture of Universal Trustwothy Network and Pervasive Services", are analyzed. By synthesizing the above research fruits, a universal network switch system USS (Universal Switch System), which is based on parallel packet switch, is proposed. USS can simultaneously support high-speed huge-capacity switch, QoS switch with coarse granularity, integrated uni- and multicast switch with changeable mix. It provides a practical switch system solution for the building of universal network. The main innovations are listed as follows:By introducing VIL and VOL in parallel packet switch and VIQ at the output of central plane, a high performance distributed parallel packet switch called BDMPPS and a practical distributed parallel packet switch called PDPPS are proposed.Based on the parallel packet switch using CICQ as central plane and DiffServ model, a distributed switch scheme called CDPPS is proposed to provide differentiated services for different traffic classes.A novel idea that constructs PPS with heterogeneous central planes is proposed, and based on this a heterogeneous parallel packet switch called HPSA is proposed to guarantee QoS with coarse granularity.Based on the idea of using different cental planes of PPS to switch unicast traffic and multicast traffic respectively, an integrated uni- and multicast switch called UMSPPS is proposed which can deal with any mix of uni- and multicast traffic.