Direct Exchange Of Variable-length Packet Switching Fabric

In recent years, variable length packet switch has been widely investigated. Cell switch has two disadvantages. First, because the packets are of variable size, so before switching, packet must be segment in to cell and be reassembled to be a packet in the output. Segmentation and reassembly (SAR) have increased the time complexity. Second, cell can generate bandwidth lost, as a cell may not contain a full packet data. For example, if a cell is of 64 bytes, a packet of 65 bytes must be segmented in two cells, and the second cell only contains one byte packet data and other padding bytes, so the mechanism of segmentation can cause serious bandwidth lost. Also, to achieving stability, internal speedup is needed. Compared to fixed length switch, by supporting variable length packet switch, there is no need for segmentation and reassembly circuits, and no speedup is necessary to support SAR.This dissertation first studies variable length packet switch in unbuffered crossbar. The first scheduling algorithm used in unbuffered crossbar supporting variable length packet is IP-PIM which is based on VOQ .When a matching of a head-of-packet cell is made, this matching is maintained until all cells of that packet have been transferred. Each packet is divided into logical cells which are not physically separated but consecutively combined. The scheduler maintains cross-point until the last logical cell named the end of packet (EOP) cell appears. The EOP cell may contain some padding overhead. This mechanism is called cell train. PB-iSLIP, SOL (Self-optimized Latency) and PB-wMWM (packet based waiting MWM) algorithms also use cell rain mechanism.With the continued increase in density of VLSI, sufficient buffering at crossbar crosspoint for one cell or packet has become feasible to implement. Buffered crossbar has been widely investigated in the recent years. Buffered crossbar natively supports variable length packet switch, because it dose not need centralized scheduler and synchronization between the input and output clock domains is simplified. This paper describes architecture of buffered crossbar working directly on variable length packet. Chapter 3 presents the simulation result, and analysis the influence of the queue length...