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High-performance Access To Parts Of The Study

Posted on:2006-01-18Degree:MasterType:Thesis
Country:ChinaCandidate:J Q RanFull Text:PDF
GTID:2208360152982395Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
Based on the research of the National Defence Preliminary Research Projects, The author primarily researched the architecture of the RISC microprocessor's Load/Store Unit and Bus Interface Unit, and applied the advanced design techniques to the "Longteng R2" RISC microprocessor.As the multi-issue and out-of-order techniques are being employed in the microprocessors, the gap between the speed of the micorprocessor and the memory further increases, therefore the overall computer system performance becomes increasingly limited by the executing efficiency of Load/Store Unit and Bus Interface Unit. This dissertation focuses on the research of techniques to improve the performance of Load/Store Unit and Bus Interface Unit. The main contributions in this dissertation are given below.1) Based on the thorough research of the PowerPC 750 instruction system and micro-architecture of "LongTeng R2" microprocessor, the Load/Store Unit of "LongTeng"R2 microprocessor is designed and implemented. By simulation and synthesis, the executing function of Load/Store Unit is compatible to PowerPC 750 Instruction system, the latency of the critical path -alignment unit is 3.24ns, which well meets the demand required by the 233MHz of "LongTengR2" clock frequency.2) Another functional unit of the "LongTeng R2" microprocessor, the Bus Interface Unit is designed and further implemented by researching the PowerPC 60X Bus Protocol. The Load/Store Buffer Model, which leads to the increasingly improved efficieny of the microprossor's access to the memory.3) The author develops the simulation environment of Load/Store Unit and Bus Interface Unit for full-instruction simulation of the microprocessor system.4) The overall verificaton system design of "LongTeng R2" FPGA implementation is completed in a single FPGA chip. The bus controller, the SRAM controller, the serial-port controller, the interrupt controller and the m2681 controller are also implemented in this FPGA chip at the same time.5) The small/big monitor program, the floating-point test program, the special instruction program packages and the VxWorks operating system's BootRom have successfully passed the test in the system.The dissertation has contributed to the success of National Defense Preliminary Research Projects and the taping out of "Long Teng R2" microprocessor.
Keywords/Search Tags:RISC, Microprocessor, Load/Store Unit, Bus Interface Unit, FPGA
PDF Full Text Request
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