The VLSI Implementation Of MQ Arithmetic Decoder

With the rapid development of computer and digital communication, research on more efficient image compression technology has been a hot point. As it's hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. In most of the image compression systems, there are always entropy encoder following the transformation unit and the quantizer. Hardware design of Entropy coding can be wildly used in real-time image compression systems.JPEG2000 is the next generation digital still image compression standard introduced by Joint Photo graphic Experts Group in December, 2000. JPEG2000 provides not only superior compression performance over JPEG but also a rich set of features, in answer to the ever growing requirements for image coding techniques. MQ encoder is adopted as JPEG2000's entropy method. It is an efficient technique for lossless data compression. But it performs slowly because of its complexity.To a certain extent ,the bottleneck of the JPEG2000 system results from the throughput of the MQ arithmetic coder and decoder. Since the decoding procedures are inherently serial processes with high dependency, arithmetic coding & decoding is very difficult to be pipeline, and the throughput is low. In this paper, theory of arithmetic coding & decoding is studied, and some important concept about binary arithmetic coding is discussed, such as multiplication-free, condition exchange and adaptive probability estimation. Then, a three level pipeline architecture of MQ decoder which can decode one symbol per clock cycle is introduced, which increased the throughput of MQ decoder. Besides, the speed bottleneck of standard decoding arithmetic is improved by some acceleration measures, such as decoding flow reduction,interval renormalization and bytein module predigestion. This architecture is described by Verilog HDL and the simulation result is correct.The whole digital system is implemented with Altera's FPGA(EP1S25B672) ,and experimental result shows that the decoder can work up to 68.0MHz on EP1S25B672 and occupy 2140 logic elements. This architecture achieves high throughput with less resources used, which can be applied in the compression field for the remote sensing image and medical image, etc.