Research And VLSI Design Of EBCOT Tier1 Encoder

As the new generation of static image compression standard, JPEG2000 adopts several new technologies, such as wavelet transform, arithmetic encoding, etc. Compared to the JPEG standard, JPEG2000 standard has many merits, including higher compression ratio, support of stream progressive transmission, encoding in interested fields, etc. EBCOT Tier1 is the core unit of JPEG2000 code, which composes of bit plane coder and MQ arithmetic coder. EBCOT Tier1 algorithm is complex, which involves a large amount of computation and costs a lot of resources and time. EBCOT Tier1 has seriously restricted the overall performance of JPEG2000 encoder, thus it is of great importance to optimize and parallel EBCOT Tier1 algorithm.Based on the optimization strategy of parallel bit plane, parallel scan channels and sample points, we analyze the algorithm of the bit plane encoder. This thesis proposes a method of part bit plane parallel which can effectively decrease the use of following class MQ arithmetic coder and optimize the channel scanning parallel code. By using the above method, the bit plane encoder VLSI design is implemented eventually, and the design effectively improves the overall performance of EBCOT Tier1 encoder.To match the bit plane encoder better, this thesis studies deeply on the principle of MQ arithmetic encoder. Firstly, five-stage pipeline architecture of MQ arithmetic coder is designed in this thesis. Then, the MQ arithmetic coder’s renormalization process and the output byte process are optimized, which effectively reduce the tedious iterative calculation during the renormalization process. Meanwhile, it is able to implement two bytes of data output in a period. Finally the thesis completes the overall design of MQ arithmetic encoder.The hardware and software verification platform is built, and the functions of bit plane coding and MQ arithmetic encoder are verified. The experimental results show that the design is correct. The synthesis, FPGA verification and static timing analysis of bit plane encoder and MQ arithmetic encoder are completed on the Spartan3-E Xilinx experimental board. Experiments show that the maximum operating frequency of bit plane encoder can reach up to 163.4 MHz. 1378 slices and 1821 registers are consumed in this hardware design. MQ arithmetic coder’s operating frequency is up to 182.15 MHz, which consumes 680 slices and 482 registers in the design. Generally speaking, the Tier1 EBCOT encoder design in this thesis has excellent performance.Finally, the digital IC front-end design is carried out in Synopsys software with 0.13 um CMOS SMIC technology. And the logic synthesis of bit plane coding and MQ arithmetic encoder is implemented.