Ipc Memory System Design

Integrate circuit is going into the SOC era. AS a result, whole embedded system can be integrated into a single die. Design and manufacture of self- copyright system level industrial PC can promote the development of our national IC industry.The work in this thesis was part of a National 05' project (project number 41308010307). and accomplished the design, implementation and verification of "LongtiumSl" memory subsystem. "LongtiumS1" has accomplished the back end design using 0.18um ASIC library, kernel voltage is 3.3v, I/O voltage is 2.5v, design working frequency is 66MHZ, tiptop working frequency is 80MHZ. Chip area is less than 25 mm2, average power consumption is 1.7W(66MHz),and is going to typeout.The research work of this thesis mainly includes:1. Analyze of "LongtiumS1 "memory subsystem, and ensure the structure of memory subsystem.2. Design and Implementation of "LongtiumS1"memory subsystem, including the Design and Implementation of SDRAM controller, DMA subsystem and the TIMER.3. Simulation and FPGA verification of "LongtiumSl" memory subsystem, including the simulation of SDRAM controller, DMA subsystem and TIMER. Accomplishing single board FPGA verification of SDRAM controller4. Design of the switch interface between "LongtiumSl" and SDRAM chip; Constructing the verification system based on this interface to run DOS OS and its applications5. Research of driver program, wear leveling strategy and data clean up strategy of DISKONCHIP for a on chip interface design for DISKONCHIP in the future. The dissertation work plays a great significance for offering designconsiderations of further SOC design.