Small Ka-band Phase-locked Source

In this thesis, a millimeter-wave phase locked frequency synthesizer is studied. The main purpose is to realize a local oscillator power with small volume and low power cost. In order to achieve these two goals, a microwave phase locked loop and a millimeter-wave multiplier is selected. The PLL (phase lock loop) is realized by form of charge pump, its loop filter is passive two-order LPF. Compared to other form of active filter, this CP PLL has less noise, which does some good to its output spectrum. The basic theory of PLL is stated, but more importance is put on the discussion of its noise spectrum and stability, even ways to improve its phase noise. Based on this analysis, loop bandwidth and damping coefficient are calculated, and debugged by experiment.The millimeter-wave quadrupler is realized by HMC283, which is actually a MMIC amplifier. It can be designed as quadrupler by offsetting its operating point of the first FET to pinchoff area. The whole circuit is mounted on RT/Duroid5880. At the output port of the multiplier, we can get the desired signal, the center frequency is 35GHz, with the step 10MHz. The signal phase noise is -60dBc/Hz@1KHz and -65dBc/Hz@10KHz. Experiment shows that a millimeter-wave synthesizer with small volume and low power cost is feasible. At the end of this thesis, some improvement of the whole system is discussed, which give a guide for further study.This research will be the technique basis of all-solid-state, all-integrated and all-coherent millimeter-wave system.