.32-bit Risc Embedded Microprocessor Design

Along with the development of manufacture technology of VLSI, IC design emphasizes reusable design and short design cycle more and more. Consequently the concept of IP (Intellectual Property) grows up, the development of many embedded modules make the design of IC simpler. MPU IP core is the typical one in these modules.To match the requirements of the kernel chips of the key IT products now time, to follow the development trend, to research the architecture of the high capability processor, a 32-bit RISC embedded microprocessor is presented in the paper, which is a VHDL model conforming to the IEEE-1754 (SPARC V8) architecture. It is designed for embedded applications with the following features: separate instruction and data caches (Harvard architecture), 5-stage pipeline, hardware multiplier and divider, interrupt controller, 16-bit I/O port and a flexible memory controller. New modules can easily be added using the on-chip AMBA AHB/APB buses. It has flexible peripheral interfaces, so can be used as an independent processor in the board-level application or as a core in the ASIC design.On the base of analyzing the SPARC instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the Harvard architecture, internal forwarding and delay branch technology.This paper presents the behavior description of ALU and the execution of most instructions, and the explanation of them. Then, presents the simulation waveforms and the synthesis result.