0.13-micron CMOS Logic Process And On-chip Integrated Passive Device Development

With the growing development of semiconductor technology, in order to obtain higher performance, semiconductor technology critical dimension is gradually reduced, which can reduce the chip area, lower the power consumption and Increase the chip speed. It enhances the chip performance and also reduces the manufacturing cost.Based on the local semiconductor manufacturing fab and the Cu line in Shanghai IC R&D center, this project developed a0.13micron CMOS logic process technology. It also developed a high quality Cu process for the integrated passive devices and SPICE models.Based on the0.13micron CMOS logic process, this project will also focus on the study of copper inductor device. The on chip integrated passive device is a new research direction. Copper inductor device is compatible with CMOS process, and it can also get a higher quality factor. With the size reduction of the device, how to make the inductor with a good performance on the inductance value and quality factor in a small size is a key point. This thesis will discuss several different layouts and different structures of the copper inductors.