Channel Estimation Algorithm And VLSI Implementation For Complex Channel Under Broadband OFDM System

OFDM (Orthogonal Frequency Division Multiplexing) is being used widely in communication field as a kind of multi-carrier modulation technology, because of its advantages such as resistance of frequency selective fading, suppression of narrowband interference and high channel utilization. The focus of this paper is channel estimation over special channels. The issues researched include how to reduce complexity of algorithm and hardware area and how to improve the algorithm performance over serious channels.The broadband OFDM communication system is very much better in throughput and bit error rate than narrowband communication system, but the cost for high performance is that the complexity of algorithm increases a lot. The complexity of resisting long echo channel estimation algorithm for DTMB system is very large, and it occupies much area. Two methods are proposed to reduce the complexity. One is via increasing the’clock frequency by25percent to get additional clock cycles and to realize reusing some key modules, and the area is reduced by32.9percent. The Other one is by simplifying the original algorithm to realize reusing some key modules when remaining the original system clock frequency and the area is reduced by45.5percent.The broadband power-line communication (BPLC) becomes a hot research topic in recent years because of its convenient access, wide distribution and low cost to establish networking. But the channel is relatively complex and there is serious impulsive noise in power lines, which is a large challenge for channel estimation. This paper studies channel estimation algorithm and noise cancellation algorithm based on the newest power-line communications standard IEEE1901. A joint interpolation method based on amplitude and phase is proposed after studying the characteristics of power-line channels and there is significant improvement in performance. The simulation results show that the BER is4*10-3when the biggest path length is300meters and it can also be on the order of magnitude of10-3even when the biggest path length is680meters at the biggest SNR. Except that the method of detecting and cancelling impulsive noise with energy of zero carriers is proposed and simulation results show that the performance is good when the impulsive noise is in the range of10to100us. In the last low complexity VLSI architecture is given and the compiling results show that it can meet the requirement of clock frequency.