Research On Receiver Algorithm In Wireless Communication And Its Implementation Based On Multi - Core Processor

As the wireless communication developed, most of the OFDM receivers implemented on the ASICs are meeting great challenges to satisfy the requirements of various standards. To quickly adapt to this variety, flexibility of software defined radio solutions have become more attractive. Most communication companies are doing this kind of research based on processors. In this paper, some research of wireless communication implementation are carrying out based on multi-core processor platform, which two typical wireless communication standards, CMMB and LTE have been studied.The major work of this thesis includes:1) Analysis the wireless communication standards worldwide at present, and survey the process platform of famous institutions both at home and abroad based on the SDR. By analysising the advantage and disadvantage of their platforms, we give out the general optimization methods of the processor platform for wireless communication.2) First, the algorithm of inner receiver in CMMB is quite mature, so we choose the typical algorithm. We first explore the degree of parallelism of algorithm, rationally partitioning the algorithm into multiple tasks at the algorithm level. Then mapping different tasks into suitable cores based on the norm of increasing the parallelism and reducing the communication cost. Further more, by using the optimization methods of SIMD, Regfile Extending, Usage of Shared Memory and Adding some complex instruction, the throughput of the inner receiver can reach up to120Mbps, which can satisfy the demand of CMMB completely. The result has absolute advantage of throughput and power effiency comparing with state of the art solutions.3) Study both the linear and non-linear algorithms of MIMO detector, especially focus on the most popular sphere algorithms, which are FD-BF and K-Best. Based on the DF-BF and the K-Best enumeration strategy, a new algorithm (KE-FDBF) is proposed. This new algorithm can reduce the visited nodes significantly with almost no symbol error rate reduction. The MIMO detector is implemented similarly to the implementation of CMMB inner receiver and combining the new feature of the Multi-Core Platform II. Further more, we optimize it by new stack methods, DMA and accelerated unit of Demap, Cordic and so on, which promote the efficiency rapidly. The implementation result is close to the ASIC result.The good implementation result of CMMB inner receiver and LTE MIMO detector due to our well mapping strategies and shows the potential of our Multi-Core Processor Platform.