Design And Realization Of Semi - Physical Simulation System Of Mid - Range Digital Array Radar

With the development of radio frequency integrated circuit and digital signal processing technology, the digital array radar(DAR) with low probability of intercept, adaptive anti-jamming ability, multi-function and software defined radio frame gets continuous development and application. In the development and debugging process of the whole digital array radar system and each subsystem, the traditional radar simulator can’t meet the requirements of DAR, such as multi channels and multi working modes. Therefore, special digital array radar simulators need to be designed.In this thesis, focused on a project of sub-array level digital array radar, a simulation system with hardware-in-the-loop is designed, which consists of a general control software and multi-channel intermediate frequency (IF) analog signal circuit. The parameters of target, jamming and noise can be flexibly seted by the general control software, and sent to the multi-channel analog IF signal circuit through gigabit ethernet in real time. A software radio approach based on FPGA+D/A is applied to the multi-channel IF analog signal circuit, to generate 36-channel IF signals containing target echo, jamming and noise, which are synchronized to the system that need to be tested. Among them,12 channels are wideband signals with the bandwidth of 30MHz,12 channels are narrowband signals with the bandwidth of 16 KHz, and the other 12 channels are narrowband signals with the bandwidth of 1.2 KHz. The target echo signals corresponding to the three kinds of emission waveforms with different pulse repetition period, can be simulated by the IF hardware-in-the-loop simulation system in various kinds of SNR and INR. The emission waveforms include, high pulse repetition frequency Pulse-Doppler wave (HPRF-PD), linear frequency modulated chirp (LFM) and linear frequency modulated continuous wave (LFMCW).The debugging results of the subsystem show that the echo signal generated by the IF hardware-in-the-loop simulation system meet the test requirements of system function and performance. Debugging results effectively verify not only the function and performance of the adaptive digital beamforming processor subsystem’s digital beamforming, but also the radar signal processor’s function and performance of target searching、confirming and tracking.