32Kb RRAM Chip Design And Layout Optimization

With the feature length kept shrinking, Flash would be faced by process bottleneck in the near future. Searching for next generation non-volatile memory has been the hotspot. Among the next generation novel non-volatile memories, Resistive Random Access Memory (RRAM) has attracted extensive focus owning to its advantages such as scalability, compatibility with standard CMOS process, low operation voltage and small cell size.RRAM chip is full custom design, the structure of memory bit and the placement, routing of other modules have strong impact on the area and resistive characteristics. So a good layout design has an important impact on the RRAM chip. For this reason, in this paper we research the RRAM layout design and the relationship between layout and characteristics such as set voltage, HRS/LRS distribution and data retention, finally optimize layout and balance the area and characteristics.We designed a32kb RRAM chip used1T1R structure. Its resistive material is WOx. Our design includes:firstly we defined the Spec, then chose the appropriate transistor and designed the smallest layout of cell. According to the cell layout and parasitic parameters such as parasitic resistance and parasitic capacitance, we designed the optimum memory array. Secondly base on the Spec, we designed the familiar and reliable peripheral circuit which includes Row decoder, Column decoder and DMA. Thirdly we optimized the layout area. At last we introduced how to choose the appropriate I/O PAD, and how to design testkey.In this paper,32kb RRAM memory chip is designed and tape out based on SMIC0.50um process. According to the test result, this chip has good resistive characteristics. HRS/LRS is larger than10X. The voltage of operation and data retention meet the Spec and practical application requirement. So good layout design can optimize area, and guarantee the resistive characteristics.