Nano-scale Integrated Circuit Modeling And Analysis Methods

Future high performance circuit design with technology scaling beyond 90nm will pose two major challenges for circuit analysis. Firstly, the wafer sizes increase and the remarkable evolution of VLSI technology enables the integration of the whore system on a single chip as is named as System-on-chip (SOC). However traditional simulators, such as SPICE, are too expensive in memory space and computation time to afford the simulation of the whole SOC chip on the transistor level. Consequently, it is very urgent to develop the effective algorithms to construct the behavioral models for each building block, since based on these models, behavioral simulation can provide the probability for the whole system verification. Secondly, as IC technology continues to advance towards nanometer dimensions, the circuit performance is increasingly less predictable because of the indetermination in the manufacturing process. To obtain the statistical information, Monte Carlo method as a direct approach is widely employed in the circuit analysis. However, the complexity of Monte Carlo analysis will become unacceptable for the circuit with very large scale. Therefore, it is quite essential to deal with the sensitivity analysis about how process parameters influence the performance of a design.For the two above significant problems, several works have been done in this dissertation and three new algorithms have been proposed, i.e., the behavioral modeling method of analog circuit blocks based on SGWD approximation, One-shot projection algorithm for model order reduction of interconnects and stochastic sparse-grid algorithm for the nonlinear circuit steady-state analysis with process variations.(1) Shannon-Gabor wavelet distributed approximation functional (SGWD), which combine Shannon sampling with a Gabor-distributed approximation functional window function, are developed for the behavioral modeling of analog circuit blocks. Two algorithms are proposed to reduce the approximation boundary errors. In the first algorithm, the approximated function is modified to make the two boundary values equal, and then the modified curve can be expanded into a periodic function. In the second algorithm, the approximated curve is expanded by even symmetry mirroring at the two boundary points. Compared with the existing polynomial approximation method, the proposed methods have less computational complexity and can reach higher accuracy.(2) In order to deal with the model order reduction for interconnects with process variations, a one-shot projection algorithm (OPM) is proposed to generate a projection matrix that is independent of statistically varying parameters. It is demonstrated that the projection subspace obtained by OPM is independent of stochastically varying parameters, and this subspace is the same one spanned by the projection matrix obtained by perturbation scheme proposed by CMU. Then, construction of the reduced system can be decoupled from Monte Carlo analysis. As a result, OPM can obtain the mean value or variance of the transfer function in frequency domain and probability density function of delay in time domain by Monte Carlo analysis not only with the same accuracy but also in much less CPU time compared with the perturbation scheme.(3) Stochastic Sparse-grid Collocation Algorithm (SSCA) is developed to analyze periodic steady-state response of the nonlinear circuits with respect to process variations. Compared with existing methods, SSCA has several important advantages. Firstly, different from Taylor expansion methods, which expand the different value range parameters, i.e., the process parameters and frequency/time parameter, with the same Taylor order, SSCA adopts disparate orthogonal bases for different kinds of parameters, i.e., Homogeneous Chaos for process variables and Fourier series or Wavelet basis in time (frequency) domain with much higher convergence rate than "Taylor expansion". Secondly, contrary to the stochastic Galerkin method which always results in high complexity for nonlinear case, SSCA has much less CPU cost since it only requires solving the deterministic nonlinear system with the same order as original ones on several selected collocation points in the process variational space. In addition, Sparse Grid technique, which is well developed in the mathematics and mechanics field, is derived in this paper to reduce the complexity of collocation algorithm. Sparse Grid technique could avoid the exponential increase of the number of collocation points generated by direct tensor product scheme in the high dimensional random space. Moreover, compared with the existing Efficient Collocation Method (ECM) developed for the gate delay modeling, which is lack of theoretical background and easily suffer from "Rank deficient problem" and "Runge phenomenon", Sparse Grid technique has the solid mathematical support and it could preserve the accuracy while reducing the number of collocation points remarkably.Some numerical examples are also given in this dissertation to demonstrate all these merits of these proposed algorithms.