Analog Device Modeling And Circuit Performance Optimization Based On Geometric Programming

With the fast developing pace of semiconductor technology, device integration and complexity of circuit design will be drastically increased. Therefore, Computer-Aided Design (CAD) for integrated circuits is greatly demanded. Device modeling, the basis of CAD, is a key research area. However, due to various undemanding low-level effects, it is difficult to accurately represent circuit performances. Although reaching high accuracy in device behavior, current BSIMv3 and BSIMv4 MOS models suffer from high complexity, since they are inherently based on high-order non-linear partial differential equations. They are, therefore, only suitable for performance verification. Currently, no modeling algorithm has been presented to balance the tradeoff between accuracy and computational effort, which is indispensable for analog synthesis and performance optimization.Analyzing current solutions of device modeling, this thesis presents a methodology based on geometric programming and convex analysis. Different from previous convex models, the methodology presented does not require apiori model functions. It instead adopts piecewise linear function to fit device parameters. Accuracy is adjustable by amount of sub-ranges. Furthermore, two fitting method, optimistic model and pessimistic model, along with response surface method, are applied to increase the flexibility.Current optimization methods can only obtain local optimum and require large amount of iterations. On the contrary, by transforming the problem into geometric programming, the methodology presented can secure global optimum with a reduced requirement of iteration.Performances of both NMOS and PMOS are investigated in this thesis. A two-stage operational amplifier is analyzed to demonstrate to effectiveness and efficiency of this methodology.