| IBM PPC405 is a 32bit RISC CPU, whose architecture is widely used in embedded environment. The SOC chip based on the XX protocol controls the circuit using IBM PPC405. This chip works in the spaceflight system, which can transmit and receive the fiber signals. This chip is the first chip, which based on the XX protocol and has the great military meanings, and economic benefit.To ensure the correctness of the RTL code according to the Power PC, the verification of it is very important. The million gates VLSI, reused IP, and SOC are so popular in our days, that verification has accounted for 70% of all the work. Verification is two times more than RTL design task. 60% of the chips are taped out two times at least. In conclusion, verification takes very important role in making a chip successfully.The author participated in all of the front verification flow, including function simulation, logic synthesization, static timing analysis, and formal verification. These verification methods took the important action on the verification of Power PC.This article's contents and the author's work are as flows:1. Building a complete testbench, including the use of System Verilog for the preparation of BFM, verification environment for the Power PC simulation, and some Testcase preparation;2. Using design for test technology based on the scan chain and ATPG technology, so that the chip taped out can be test effectively;3. Completing the static timing analysis using PT to check whether the timing to meet the timing requirements;4. Doing the formal verification using Formality to complete the RTL and netlist contrast, and ensure the functional consistency.This article also expatiates the theory of functional verification, logic synthesis, STA and formal verification; The universal and fast testbench is made based on the SystemVerilog; The highly automatic scripts are made to synthesis, STA and formal verification; The front verification flow is made reasonable for the MCU. |
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