.0.16 Micron Logic Sram Lithography Process Parameters, Optimization Studies

The improvement and optimization of the photolithography process for 0.16um SRAM logic was discussed. This will help point out the keystone of process control for DUV photolithography, especially for carried SRAM working area product.For this product, three main problems were analyzed in detail and got the solution finally. This product also has been implement mass production successfully. The follow will list four problems.1. Overlay matching issue at ACT front end of layer In the most popular 0.16um SRAM product, ACT layer is always the first layer, there is no pre-layer issue for ACT but it's self alignment will induce following layer's overlay matching issue in lithography process control, especial for the SRAM working area. In this chapter, we will discuss the photo overlay alignment principle and overlay modeling analysis, and give out the solution for ACT layer SRAM area overlay jump issue.2. The SRAM area pattern broken and scum optimizing It is critical for SRAM area CD concern, and in this chapter we will discuss from the special design of 0.16um SRAM pattern to analysis the process improvement for pattern broken and scum. Then develop a new weak point system to avoid the similar case happen again in FAB.3. Satellite defect introduction and the solution for 0.16um SRAM logic circuit. In current process for 0.16um SRAM logic circuit, it is easily suffer the satellite defect in the our process, and worse defect will impact the yield ratio. In this chapter we will use the post exposure bake method to solve the satellite defect.